1. Field of the Invention
This invention relates to a signal amplification circuit for electrical and electronic equipment, used in automobiles, two-wheeled motor vehicles, and in industry, and in particular relates to a signal amplification circuit of a semiconductor physical quantity sensor used in automobiles and two-wheeled motor vehicles.
2. Description of the Related Art
At present, in the fields of automobiles and two-wheeled motor vehicles, there is an accelerating move toward control by electrical and electronic components of portions that heretofore had been controlled by mechanical components.
Moreover, electronic component products used in the past are becoming increasingly precise and multifunctional, aiming at more sophisticated control.
For example, pressure sensors used to measure the pressure within an intake manifold or to measure brake hydraulic pressure are now required to have a function to detect their own malfunction (a diagnostic function), in addition to a function for measuring and outputting the pressure.
FIG. 6 shows the configuration of principal portions of a pressure sensor of the prior art. The pressure sensor comprises a signal amplification circuit 10c including an op-amp 41; a pressure is converted into an electrical signal by the piezoelectric effect in the pressure detection portion, this electrical signal is inputted to positive and negative input terminals 011 and 012 processed by the signal amplification circuit 10c, and the processed signal is output from an output terminal 02 of the signal amplification circuit 10c (which is also an output terminal of the pressure sensor) to an ECU (Engine Control Unit).
The diagnostic function enables the sensor itself to detect breakage of wiring connecting the pressure sensor to the ECU (breakage of a wire bonding wire, lead frame, wiring harness, or similar), and transmits this information to the ECU; by means of this function, in the unlikely event of a malfunction the malfunction can be detected, and a failsafe function can ensure that a major problem is prevented.
FIG. 7 is a conceptual diagram (graph) representing output characteristics and diagnostic functions of a pressure sensor. The X axis indicates the pressure (in kPa) measured by the sensor, and the Y axis indicates the output voltage (in V) output from the pressure sensor. The following explanation is of a general nature; a more detailed explanation is given later.
Until now, pressure sensors not having diagnostic functions have had only functions to output only certain determined voltages according to the measured pressure, and specifically, to output voltages in the range Vb to Vc in FIG. 7 (the steady output range).
On the other hand, a pressure sensor having a diagnostic function employs a mode in which voltages equal to or lower than the output Va and equal to or greater than the output Vd of the pressure sensor (diagnostic regions) are output when breakage of a wire or similar occurs, in addition to the above-described steady output range; when a voltage in a diagnostic region is received by the ECU, an anomalous state of the pressure sensor is detected.
Here, in order to realize a diagnostic function for a pressure sensor, the following two engineering means are necessary.
(1) Means for outputting a voltage in a diagnostic region when breakage of a wire, wiring harness, or similar occurs
(2) Means for not outputting a voltage in a diagnostic region when the pressure sensor is in the normal state
The means (1) is disclosed in Japanese Patent Application Laid-open No. 2003-304633, and is here omitted.
Next, with respect to the means (2), in the prior art, utilization of the saturation voltage of a signal processing signal (e.g., output operational amplifier: op-amp 41 in FIG. 6) is the method most generally used.
FIG. 8 is a circuit diagram of a signal processing circuit used as a general signal processing circuit for a pressure sensor. This signal processing circuit 10c is a negative feedback amplification circuit 40, comprising a differential amplifier circuit 40a and a resistor 46; the differential amplifier circuit 40a comprises an op-amp 41 and five resistors 42, 43, 44, 45, 46. As the input/output terminals, a positive input Vin+ terminal 011, a negative input Vin− terminal 012, and an output terminal Vout 02, as well as a third reference voltage source 70 serving as an offset voltage, are provided.
The resistors 44 and 45 are connected in series between the Vin+ terminal 011 and the third reference voltage source 70, and the connection point between the resistors 44 and 45 is connected to the non-inverting input terminal (+ terminal) of the op-amp 41.
The resistors 42, 43, 46 are connected in series between the Vin− terminal 012 and the output terminal 41b of the op-amp 41. The connection point between the resistors 42 and 43 is connected to the inverting input terminal (+ terminal) of the op-amp 41, and the connection point 40c between the resistors 43 and 46 is connected to the Vout terminal 02.
The output voltage Vout of the signal amplification circuit 10c can be approximately determined using the equation below. If Vout is the voltage at the Vout terminal 02, Vin+ is the voltage at the Vin+ terminal 011, Vin− is the voltage at the Vin− terminal 012, R43 is the resistance value of the resistor 43, R42 is the resistance value of the resistor 42, and Vref3 is the voltage of the third reference voltage supply 70, thenVout=(Vin+−Vin−)×(R43/R42)+Vref3
In this signal amplification circuit 10c, the upper-limit saturation voltage and lower-limit saturation voltage of the output are determined by the upper- and lower-limit saturation voltages of the op-amp 41 and by the voltage drop occurring across the resistor 46. More specifically, the above-described two means depend on the following elements.
(Upper- and lower-limit saturation voltages of op-amp 41)
(1) Saturation voltage of transistors used in the output stage of the op-amp 41
(2) Impedance component of transistors used in the output stage of the op-amp 41
(Voltage drop occurring across the resistor 46)
(3) Resistance value of the resistor 46
(4) Current flowing in the resistor 46 (approximately equal to the load current flowing into/out of the Vout terminal 02)
FIG. 9 and FIG. 10 explain the lower-limit saturation voltage and upper-limit saturation voltage of the output. FIG. 9 and FIG. 10 use the same reference numerals as each other. Also, the same elements as in FIG. 8 are denoted by the same reference numerals as in FIG. 8.
In FIG. 9, Tr1 and Tr2 are transistors of the output stage 41a of an op-amp 41. The lower-limit saturation voltage of the output is the voltage resulting from adding to ground GND, that is 0 V, which is the source potential of the output-stage transistor Tr2 (a MOSFET) of the op-amp 41 of FIG. 9, (1) the voltage V5 of Tr2 which includes the on-stage voltage of the output-stage transistor Tr2 (MOSFET) of the op-amp 41 and the impedance of Tr2, occurring due to a sink current I03 in the op-amp 41, and (2) the voltage V6 occurring across the resistor 46 due to a current I7 flowing in from the load side; the resulting voltage is approximately 0.2 V.
On the other hand, in FIG. 10 the output upper-limit saturation voltage is the drain voltage of the transistor Tr1 (MOSFET), which is the power supply voltage VDD, that is, approximately 5 V, and so the voltage is the result of subtracting (1) the voltage V4 resulting by adding the on-state voltage of the transistor Tr1 (MOSFET) in which the source current I13 of the op-amp 41 occurs and the voltage due to the impedance of Tr1, and (2) the voltage V7 occurring across the resistor 46 due to a current I8 flowing out to the load side, and is approximately 4.8 V.
As explained above in FIGS. 8-10, in the case of a conventional signal amplification circuit 10c, elements determining the output saturation voltage depend on the characteristics of the transistors Tr1 and Tr2 comprised by the op-amp 41 and the resistance value of the resistor 46. For example, if the resistance value of the resistor 46 and the voltages V4 and V5 of Tr1 and Tr2 are low, the lower-limit saturation voltage falls, and the upper-limit saturation voltage rises. Conversely, if these values are high the lower-limit saturation voltage rises and the upper-limit saturation voltage falls.
In this way, the lower-limit saturation voltage and upper-limit saturation voltage depend on the characteristics of the transistors Tr1, Tr2 comprised by the op-amp 41 and the value of the resistor 46, and so fluctuations in the lower-limit saturation voltage and upper-limit saturation voltage easily occur due to “manufacturing variance” during manufacturing and due to “temperature dependence” thereof, and it is difficult to suppress the variance in these saturation voltages. In FIG. 9 and FIG. 10, the current flowing in the resistor 46 includes the current I7 flowing in from the load side and the current I8 flowing out to the load side, indicated by dotted lines; but in the above explanation these have been omitted. Tr1 in FIG. 9 and FIG. 10 may also be a p-channel MOSFET.
The effect on the pressure sensor output characteristics of the above-described manufacturing variance and temperature dependence is explained, again using FIG. 7. In FIG. 7, the target pressure sensor output is represented by the solid line b. There is a saturation voltage region (a region in which the voltage is constant; the constant voltage is the saturation voltage) is outside the steady output region, and moreover inside the diagnostic region. Most of lower-limit saturation voltages are positioned within the range Va to Vb (Δ1), while most of upper-limit saturation voltages are positioned within the range Vc to Vd (Δ2).
In the steady output range, a voltage is output which is linear with respect to the pressure, and when the pressure sensor is in steady operation (when there is no breakage of wiring or similar), in a case in which some excessively high pressure (or excessively low pressure) acts, due to some case other than a malfunction, so as to fall outside the steady range, it is desirable that the pressure sensor continue operation. Hence it is desirable that the output of the signal amplification circuit 10c in FIG. 8 saturate in a voltage interval not reaching a diagnostic region, that is, in the range Va to Vb and the range Vc to Vd.
However, due to the effect of the above-described “manufacturing variance” and “temperature dependence”, when the output voltage range of the signal amplification circuit 10c in FIG. 8 has become broad (does not readily reach saturation), the output voltage is as indicated by the dotted line a. The output characteristic of the dotted line a is such that the saturation voltage is positioned in a diagnostic region, so that even when the pressure sensor is in steady operation, cases occur in which the saturation voltage enters into a diagnostic region, and in this case the problem arises that the ECU misdiagnoses the situation as a “sensor malfunction”.
Conversely, when the output voltage range of the signal amplification circuit 10c in FIG. 8 becomes narrow (saturation easily occurs), the shape is as indicated by the dotted line c, and saturation occurs in the region in which a voltage which is linear with respect to pressure should be output (the region close to Vb and Vc), and there is the problem that the original function of a pressure sensor cannot be performed.
One means to avoid the above problems is to provide a diagnostic region and a steady output range, taking into consideration the range of variation in the saturation voltage due to manufacturing variance and temperature dependence. That is, to broad intervals Va to Vb and Vc to Vd such that variation in the saturation voltage of the output characteristic can be absorbed.
However, the range of variation of saturation voltage for a conventional signal amplification circuit 10c (in FIG. 8) is too broad to be absorbed. As one example, the graph of FIG. 11 shows the manufacturing variation range and temperature dependence of the lower-limit saturation voltage in a signal amplification circuit 10c in an example of the prior art. The X axis indicates temperature (° C.), the Y axis indicates the lower-limit saturation voltage (V), MAX indicates values of lower-limit saturation voltage which are highest due to manufacturing variation, TYP indicates values of the lower-limit saturation voltage which are as per typical design, and MIN indicates values of the lower-limit saturation voltage which are lowest due to manufacturing variation.
From FIG. 11, it is seen that the lower-limit saturation voltage of the signal amplification circuit 10c in FIG. 8 has variation of approximately 70 mV due to temperature and approximately 70 mV due to manufacturing variation, for a total variation of approximately 140 mV. In this example, measurements are performed at a power supply voltage=5 V. That is, for a power supply voltage of 5 V a variation of 140 mV=2.8% variation range over the entire range, which is not a small value. Of course a similar variation range occurs for the upper-limit saturation voltage.
In order to decrease this large variation range, manufacturing variation in the characteristics (on-state voltage, impedance, and similar) of the transistors Tr1, Tr2 of the op-amp 41 and of the resistance value of the resistance 46 (in FIGS. 8-10) must be decreased. The manufacturing variation can be decreased through measures taken in pressure sensor characteristic selection and manufacturing methods, but increases in manufacturing costs result. On the other hand, temperature dependence is related to the temperature dependences specific to materials, and so is not easily reduced.
In order to resolve these problems, Japanese Patent Application Laid-open No. 2007-312368 and Japanese Patent Application Laid-open No. H7-209326 disclose signal amplification circuits which are not easily affected by manufacturing variation or temperature dependence of the components (transistors, resistors, and similar), and which have small variation of the saturation voltage, which is an output characteristic.
FIG. 12 shows the configuration of a signal amplification circuit disclosed in Japanese Patent Application Laid-open No. 2007-312368. The signal amplification circuit 10a comprises a negative feedback amplification circuit 40, a lower-limit voltage limiting circuit 20, and an upper-limit voltage limiting circuit 30; the negative feedback amplification circuit 40 comprises a differential amplification circuit 40a, and a resistor 46 and the differential amplification circuit 40a comprises a Vin+ terminal 011, a Vin− terminal 012, first to third reference voltage sources 50, 60, 70, an op-amp 41, and four resistors 42 to 45. The lower-limit voltage limiting circuit 20 comprises an op-amp 21 and a diode 22 for backflow prevention; the upper-limit voltage limiting circuit 30 comprises an op-amp 31 and a diode 32 for backflow prevention. The output terminal (Vout terminal 02) of the signal amplification circuit 10a is connected to the output terminal 40b of the negative feedback amplification circuit 40, and the output terminal 40b is connected to the connection point 40c of the resistor 43 and the resistor 46. In the figure, 41b is the output terminal of the op-amp 41; the output terminal 41b and one end of the resistor 46 are connected, and the other end of the resistor 46 is connected to the connection point 40c. 
In the lower-limit voltage limiting circuit 20, the non-inverting input terminal (+ terminal) of the op-amp 21 is connected to the first reference voltage source 50, and the inverting input terminal (− terminal) of the op-amp 21 is connected to the Vout terminal 02. The output terminal of the op-amp 21 is connected to the anode terminal of the diode 22, and the cathode terminal of the diode 22 is connected to the Vout terminal 02.
And, in the upper-limit voltage limiting circuit 30, the non-inverting input terminal (+ terminal) of the op-amp 31 is connected to the second reference voltage source 60, and the inverting input terminal (− terminal) of the op-amp 31 is connected to the Vout terminal 02. The output terminal of the op-amp 31 is connected to the cathode terminal of the diode 32, and the anode terminal of the diode 32 is connected to the Vout terminal 02.
By means of this configuration, the effects of the manufacturing variation and temperature dependence of each component (transistors, resistors, and similar) are not easily felt, and variation in the saturation voltage, which is an output characteristic, is reduced.
FIG. 13 shows the configuration of a signal amplification circuit disclosed in Japanese Patent Application Laid-open No. H7-209326. In FIG. 13, the signal amplification circuit comprises bipolar transistors Q0-Q19, resistors R1-R15, a MOS transistor M1, a constant-current source I1 and a capacitor C1. A reference voltage is created by Q18, Q19, R13, R14, and R15; Q14 and Q15 are transistors used for voltage limiting, and the above-described reference voltage is input to the bases of Q14 and Q15.
In steady operation, Q14 and Q15 are turned off (non-conducting), and when the output of the op-amp falls below the Vbe (base voltage) of −Q14 at the voltage-dividing point of R14 and R15, Q14 transitions to the on state, current flows into the op-amp, and control is executed such that the voltage Vout does not fall below this.
On the other hand, when the output of the op-amp exceeds the Vbe of +Q14 at the voltage-dividing point of R13 and R14, Q15 transitions to the on state. Current is drawn from the op-amp, and control is executed such that the voltage Vout does not rise above this.
FIG. 14 shows the configuration of a signal amplification circuit 31 disclosed in Japanese Patent Application Laid-open No. 2005-328151. In FIG. 14, VDD and VSS indicate the high and low potential side of a power supply, respectively. In this configuration, even when no switching circuit or similar is provided in particular, when the output voltage Vout is higher than a lower-limit limiting voltage VL, operation of the op-amp 16 becomes dominant, and inverted amplification can be performed without impeding operation of the op-amp 17.
On the other hand, it is stated that when the output voltage Vout is lower than the lower-limit limiting voltage VL, operation of the op-amp 17 becomes dominant, and precise lower-limit clamping operation can be performed without impeding operation of the op-amp 16.
Similarly, the op-amp 16 and the op-amp 27 are configured as negative feedback circuits, which take as inputs to the inverting input terminals the output voltage Vout so as to perform a higher-limit clamping operation with a higher-limit limiting voltage VH. The phase compensation circuits 22, 25, 30 of the op-amps 16, 17, 27 are connected to the output terminal Vout.
In the method disclosed in Japanese Patent Application Laid-open No. 2007-312368 as shown in FIG. 12, a source current flowing from the lower-limit voltage limiting circuit 20 to the negative feedback amplification circuit 40 when fixing (clamping) the output voltage. And, a sink current drawn from the negative feedback amplification circuit 40 to the upper-limit voltage limiting circuit 30 is necessary.
Further, in the method disclosed in Japanese Patent Application Laid-open No. H7-209326 as shown in FIG. 13, at the time of clamping operation is performed to either pass current to or draw current from the op-amp, and the current consumption is increased due to clamping.
That is, in the methods disclosed in Japanese Patent Application Laid-open No. 2007-312368 and Japanese Patent Application Laid-open No. H7-209326, when it is necessary to increase the sink/source capacity of the negative feedback amplification circuit, for example in low-resistance load driving or similar, the current consumption increases dramatically. And when the value of the upper-limit limiting voltage is low and the value of the lower-limit limiting voltage is high, current consumption increases dramatically.
In the method disclosed in Japanese Patent Application Laid-open No. 2005-328151 as shown in FIG. 14, it is stated that an unstable state due to collision between operation of the op-amp 16 and the op-amp 17 does not occur; but in actuality, collision occurs due to operation of the op-amp 16 and the op-amp 17, and there is a strong possibility that the op-amps may enter an unstable state. This is explained using FIG. 14 and FIG. 15.
For example, in FIG. 14, with approximately the timing at which the output voltage Vout passes the lower-limit limiting voltage VL or other voltage for clamping, there is transient repetition of (1) overshooting of the voltage falling, due to the response speeds of the op-amps 16 and 17, (2) consequent voltage rising due to the feedback II, (3) overshooting of the voltage rising, due to the response speeds of the op-amps 16 and 17, (4) consequent voltage falling due to the feedback I, and (5) a return to (1), so that the voltage oscillates.
In this transient region, the op-amp 16 and op-amp 17 are both in an active state, and a collision state occurs. When the response speeds of the op-amp 16 and the op-amp 17 are about the same, oscillation continues near the lower-limit limiting voltage VL, as shown in FIG. 15, and operation of the op-amps 16, 17 becomes unstable.
In this transient state, given the circuit configuration of FIG. 14, the following problem arises. The op-amp 16 and op-amp 17 both have output Vout connected to the phase compensation circuit 22 and phase compensation circuit 25, to perform phase compensation of the output Vout. In this case, the optimum phase compensation values differ in the transient region in which feedback I shown in FIG. 15 dominates and in the transient region in which feedback II dominates. Specifically, when performing phase compensation of op-amp 17, the current flowing in N8 must also be taken into consideration, but the current flowing in N8 cannot be controlled solely by the op-amp 17, but also depends on the state of N4 controlled by the op-amp 16. That is, the optimum phase compensation value for op-amp 17 changes with the state of op-amp 16, and consequently calculation of the values of the resistors and capacitors in the phase compensation circuit 25 becomes extremely complex. Also, for similar reasons, due to the effect of N4 on the op-amp 17, calculation of the values of the resistors and capacitors in the phase compensation circuit 22 for op-amp 16 becomes extremely complex.
The above are details of the collision state; due to this complexity, in the actual circuits unstable time periods tend to occur. Further, when performing phase compensation of the op-amp 17, current flowing in N8 that affects the op-amp 16 must also be considered, and calculation of the values of the resistors and capacitor of the phase compensation circuit 25 becomes complex.